High Speed Low Power Scalable Programmable Dual Modulus Digital CMOS Frequency Dividers

A high-speed low power scalable programmable dual modulus digital CMOS frequency divider architecture is proposed. The unique frequency divider architecture includes a high speed parallel counter with State Excitation Module, a switchover trigger circuit, a modulus switchover circuit and a reloader circuit. The mode switchover circuit has two sets of external programmable inputs for two alternative frequency select/modulus select. The reload circuit consists of a DFF, an inverter and a two input NAND gate. The reload circuit resets the parallel counter upon receiving the trigger pulses from the mode switch over circuit. Thus, the dual modulus digital CMOS frequency divider sequences through two alternative cycles and the number of states in each cycle is determined by the respective external inputs. Initially, the proposed dual modulus digital CMOS frequency divider was constructed using the existing parallel counter architecture [1]. Then, to improve the performance of the frequency divider circuit two different types of 8-bit counter architectures were proposed. The proposed dual modulus digital CMOS frequency divider using these two architectures provides improved performance compared to the same circuit by using the existing counter architecture. The 8-bit divider using the existing parallel counter architecture consumed a total transistor count of 780 whereas the same circuit using the proposed parallel counters consumed only 612 transistors. The power dissipation for divider using the existing parallel counter architecture and the proposed parallel counter architecture were 4.21mW (PINT) and 3.60mW (PINT) respectively at 250MHz. The worst case delay observed for divider using the existing parallel counter architecture and the proposed parallel counter architecture were 7.179ns and 7.164ns respectively using Altera Quartus II. Keywords—Counter, divide-by-N, frequency divider, high speed, low-power, modules, modulus